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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. november 1994 copyright ? intel corporation, 1995 order number: 272271-002 8xc51sl/low voltage 8xc51sl keyboard controller 80c51sl e cpu with ram and i/o; v cc e 5v g 10% 81c51sl e 16k rom preprogrammed with systemsoft keyboard controller and scanner firmware. v cc e 5v g 10%. 83c51sl e 16k factory programmed rom. v cc e 5v g 10%. 87c51sl e 16k otp rom. v cc e 5v g 10%. low voltage 80c51sle cpu with ram and i/o; v cc e 3.3v g 0.3v low voltage 81c51sle 16k rom preprogrammed with systemsoft keyboard controller and scanner firmware. v cc e 3.3v g 0.3v. low voltage 83c51sle 16k factory programmed rom. v cc e 3.3v g 0.3v. low voltage 87c51sle 16k otp rom. v cc e 3.3v g 0.3v. y proliferation of 8051 architecture y complete 8042 keyboard control functionality y 8042 style host interface y optional hardware speedup of gatea20 and rcl y local 1 6 x 8 keyboard switch matrix support y two industry standard serial keyboard interfaces; supported via four high drive outputs y 5 led drivers y low power chmos technology y 4-channel, 8-bit a/d y interface for up to 32 kbytes of external memory y slew rate controlled i/o buffers used to minimize noise y 256 bytes data ram y three multifunction i/o ports y 10 interrupt sources with 6 user- definable external interrupts y 2 mhz 16 mhz clock frequency y 100-pin pqfp (8xc51sl) 100-pin sqfp (low voltage 8xc51sl) the 8xc51sl, based on intel's industry-standard mcs 51 microcontroller family, is designed for keyboard control in laptop and notebook pcs. the highly integrated keyboard controller incorporates an 8042-style upi host interface with expanded memory, keyboard scan, and power management. the 8xc51sl supports both serial and scanned keyboard interfaces and is available in pre-programmed versions to reduce time to market. the low voltage 8xc51sl is the 3.3v version optimized for even further power savings. throughout the remainder of this document, both devices will generally be referred to as 51sl. the 8xc51sl is a pin-for-pin compatible replacement for the 8xc51sl-bg. it does, however have some additional functionality. those additional functions are as follows: 1. 16k otp rom: the 8xc51sl-bg had only 8k of rom. 2. new register set: the 8xc51sl adds a second set of host interface registers available for use in support- ing power management. this required an additional address line (a1) for decoding. to accommodate this, one v cc pin was removed. however, in order to maintain compatibility with the -bg version, an enable bit for this new register set was added in configuration register 1. this allows the 8xc51sl to be drop in compatible to existing 8xc51sl-bg designs; no software modifications required. note: the changes made to the v cc pins require that all three v cc pins be properly connected. failing to do so could result in high leakage current and possible damage to the device.
8xc51sl/low voltage 8xc51sl 272271 1 figure 1. block diagram 2
8xc51sl/low voltage 8xc51sl 272271 2 figure 2. connection diagram (pqfp and sqfp) packages part prefix suffix package type 8xc51sl ku ah 100-pin pqfp low voltage 8xc51sl sb al 100-pin sqfp 3
8xc51sl/low voltage 8xc51sl pin descriptions table 1. pin descriptions symbol type description v ss circuit ground potential. v cc supply voltage during normal, idle, and power-down operation; nominally a 5v g 10% for 8xc51sl, a 3.3v g 0.3v for low voltage 8xc51sl. pcdb0 7 i/o host interface data bus. an 8-bit bidirectional port for data transfers between the host processor and the keyboard controller. wrl i the active-low, host-interface write signal. rdl i the active-low, host-interface read signal. csl i the active-low, host-interface chip select. a0 a1 i host-interface address select inputs. pcobf o the active-high, host-interface output buffer full interrupt. gatea20 o gate a20 control signal output. rcl/progl o host reseteactive low. this pin is also the program pulse input during eprom programming. led0 3 o led output drivers. ksi0 7 i keyboard input scan lines (input port 0). schmitt inputs with 5k 20k pull-up resistors. kso0 15 o keyboard output scan lines. port 1 i/o port 1 is a general-purpose, 8-bit bidirectional port with internal pull-ups. it also supports the following user-selectable functions: p10/a0 p10 p16 are available for connection to dedicated keyboard inputs. a0 a7 output the low-order address byte (refer to loadren signal). p17/a7 loadren i low address enable. when set high, address bits a0 a7 are output on p10 p17. port2 i/o port 2 is a general-purpose, 8-bit bidirectional port with internal pull-ups on p20 6/ a8 14. it also supports the following user-selectable functions: p20 6/a8 14 p20 6/a8 14 output the high-order address byte. p27/led4 p27/led4 is available as a fifth led output driver (by writing to the port bit 7). port 3 i/o port 3 is a general-purpose, 8-bit bidirectional port. p32/int0, p34/t0, p36/wrl, and p37/rdl have internal pull-ups. p30/sif00, p31/sif01, p33/sif10, and p35/sif11 are high-drive open-drain outputs. it also supports the following user- selectable functions: p30/sif00 a high-drive, open-drain output to support an external serial keyboard interface (typically clk); rxd (8051 uart serial input port); sif0intl (serial interface interrupt 0). p31/sif01 a high-drive, open-drain output to support an external serial keyboard interface (typically data); txd (8051 uart serial output port). p32/int0 int0l (external interrupt 0). p33/sif10 a high-drive, open-drain output to support an external serial keyboard interface (typically mouse clk); sif1intl (external interrupt 1). p34/t0 auxobf1 (output buffer fullemouse support); t0 (timer/counter 0 external input). p35/sif11 a high-drive, open-drain output to support an external serial keyboard interface (typically mouse data); t1 (timer/counter 1 external input). p36/wrl wrl (external data memory write strobe); inactive at addresses 7ff0 7fffh. p37/rdl auxobf2 (output buffer full interrupt); int2l (external interrupt); rdl (external data memory read strobe); inactive at addresses 7ff0 ffffh. 4
8xc51sl/low voltage 8xc51sl pin descriptions (continued) table 1. pin descriptions (continued) symbol type description xtal1 i input to the on-chip oscillator. xtal2 o output from the on-chip oscillator. avgnd analog ground potential. avref analog supply voltage; nominally a 5v g 10% for 8xc51sl, a 3.3v g 0.3v for low voltage 8xc51sl. ain0 3 i a/d analog input channels. adb0 7 i/o external address/data bus. multiplexes the low-address byte and data during external memory accesses. eal/v pp i external address input. when held high, the 51sl cpu executes out of internal program memory unless the program counter exceeds 3fffh. when held low, the 51sl cpu always executes out of external memory. eal is latched on the falling edge of rst. this pin also receives the programming supply voltage (v pp ) during eprom programming. ale o address latch enable output pulse latches the low address byte during external memory access. ale is output at a constant rate of (/6 the oscillator frequency, whether or not there are accesses to external memory. one ale pulse is skipped during the execution of a movx instruction. ale is disabled during idle mode and can also be disabled via configuration register 1 control. psenl o program store enable is the read strobe to external program memory. psenl is qualified with rdl and a15 for use with an external flash memory. psenl is not active when the device executes out of internal program memory. memcsl i/o external memory chip select for code space address 4000h and above, when eal is inactive (i.e., high). for eal low, memcsl is active. goes inactive during idle mode and power-down mode. if external memory interfacing is not required, memcsl can be configured as a general purpose i/o (controlled via configuration register 1). rst i resets the keyboard controller. hold rst high for two machine cycles. 5
8xc51sl/low voltage 8xc51sl 8xc51sl/low voltage 8xc51sl pin characteristics table 2. pin characteristics pin no. pin name type term reset pd mode 1 kso0 o od tri hold 2 kso1 o od tri hold 3 kso2 o od tri hold 4 kso3 o od tri hold 5 kso4 o od tri hold 6 kso5 o od tri hold 7 kso6 o od tri hold 8 kso7 o od tri hold 9 kso8 o od tri hold 10 kso9 o od tri hold 11 kso10 o od tri hold 12 kso11 o od tri hold 13 v ss 14 v cc 15 kso12 o od tri hold 16 kso13 o od tri hold 17 kso14 o od tri hold 18 kso15 o od l hold 19 ksi0 i 5k 20k pu nc 20 ksi1 i 5k 20k pu nc 21 ksi2 i 5k 20k pu nc 22 ksi3 i 5k 20k pu nc 23 ksi4 i 5k 20k pu nc 24 ksi5 i 5k 20k pu nc 25 ksi6 i 5k 20k pu nc 26 ksi7 i 5k 20k pu nc 27 ale o l l 28 memcsl o l (eal e 0) h 29 psenl o l l 30 p10/a0 i/o pu wh hold 31 p11/a1 i/o pu wh hold 32 p12/a2 i/o pu wh hold 33 p13/a3 i/o pu wh hold 34 p14/a4 i/o pu wh hold 35 p15/a5 i/o pu wh hold 36 p16/a6 i/o pu wh hold 37 p17/a7 i/o pu wh hold 6
8xc51sl/low voltage 8xc51sl 8xc51sl/low voltage 8xc51sl pin characteristics (continued) table 2. pin characteristics (continued) pin no. pin name type term reset pd mode 38 v ss 39 v ss 40 adb0 i/o tri tri 41 adb1 i/o tri tri 42 adb2 i/o tri tri 43 adb3 i/o tri tri 44 adb4 i/o tri tri 45 adb5 i/o tri tri 46 adb6 i/o tri tri 47 adb7 i/o tri tri 48 p20/a8 i/o pu wh hold 49 p21/a9 i/o pu wh hold 50 p22/a10 i/o pu wh hold 51 p23/a11 i/o pu wh hold 52 p24/a12 i/o pu wh hold 53 p25/a13 i/o pu wh hold 54 p26/a14 i/o pu wh hold 55 p27/led4 i/o od tri hold 56 v ss 57 gatea20 o wh hold 58 pcdb7 i/o tri tri 59 pcdb6 i/o tri tri 60 pcdb5 i/o tri tri 61 pcdb4 i/o tri tri 62 pcdb3 i/o tri tri 63 pcdb2 i/o tri tri 64 rcl/progl o wh hold 65 v cc 66 pcdb1 i/o tri tri 67 pcdb0 i/o tri tri 68 rst i 69 xtal2 o h 70 xtal1 i 71 pcobf o l hold 72 csl i 73 rdl i 74 wrl i 7
8xc51sl/low voltage 8xc51sl 8xc51sl/low voltage 8xc51sl pin characteristics (continued) table 2. pin characteristics (continued) pin no. pin name type term reset pd mode 75 a0 i 76 ain3 i 77 ain2 i 78 ain1 i 79 ain0 i 80 avref 81 avgnd 82 v cc 83 v ss 84 p37/rdl i/o pu wh hold 85 p36/wrl i/o pu wh hold 86 p35/sif11 i/o od tri hold 87 p34/t0 i/o pu wh hold 88 p33/sif10 i/o od l hold 89 p32/int0 i/o pu wh hold 90 p31/sif01 i/o od tri hold 91 p30/sif00 i/o od l hold 92 a1 i 93 v ss 94 eal i 95 loadren i 96 v ss 97 led3 o od tri hold 98 led2 o od tri hold 99 led1 o od tri hold 100 led0 o od tri hold notes: 1. during power down mode all floating i/o pins or inputs without internal pullups should be driven. 2. pu e pulled up, od e open drain, wh e weak high, tri e tri-state. 8
8xc51sl/low voltage 8xc51sl port structures and operation all three 51sl ports are bidirectional. each consists of a latch (special function registers p1 through p3), an output driver, and an input buffer. port 0 of the 51sl cpu does not connect to the package pins. it is used internally to drive the keyboard scan logic. the output drivers of ports 1 and 2 can be used in accesses to external memory. the 51sl provides the loadren signal to facilitate external memory interfaces. when the loadren signal is high, port 1 outputs the low byte of the external memory ad- dress. if loadren is tied low, then the port 1 sig- nals continue to emit the p1 sfr content. port 2 outputs the upper seven bits of the high byte of the external address when the address is 15 bits wide and either eal is tied low or eal is tied high and bit 0 (addren) of configuration register 1 is set. other- wise, the port 2 pins continue to emit the p2 sfr content. i/o configurations all port pins with the exception of p27/led4, p30/sif00, p31/sif01, p33/sif10, and p35/sif11 have fixed internal pullups and therefore are called ``quasi-bidirectional ports''. when configured as in- puts, the pins are pulled high by the pullups and will source current when externally pulled low. during a 15-bit external program memory access, port 2 outputs the high address byte. in the 80c51 the port 2 drivers use the strong pullup during the entire time that they are emitting a ``1'' on a port 2 bit. in this instance, the 80c51 weak quasi-bidirec- tional pullup condition that normally occurs after two oscillator periods does not occur. port 1 and port 2 of the 51sl emulate the quasi-bidirectional pullup condition during program memory access, not this extended strong pullup condition. power management the 51sl uses low power chmos and provides for two further power savings modes, available when in- active: idle mode, typically between keystrokes; and power down mode, upon command from the host. a four channel, eight-bit a/d converter is also includ- ed for power management (i.e., battery voltage/tem- perature monitoring, etc.). idle mode idle mode is initiated by an instruction that sets the pcon.0 bit (sfr address 87h) in the 51sl. in idle mode, the internal clock signal to the 51sl cpu is gated off, but not to the interrupt timer and serial port functions. the 51sl status is preserved in its entirety: the stack pointer, program counter, pro- gram status word, accumulator, and all other regis- ters maintain their data. the port pins hold the logic levels they had when idle mode was activated. ale and psenl are held high. if an a/d conversion is in process when idle mode is entered, any conversion results may contain erroneous data. idle mode is ex- ited via a hardware reset, or an enable interrupt. power down mode power down mode is initiated by an instruction that sets bit pcon.1 in the 51sl cpu. when the 51sl enters power down mode, all internal clocks, includ- ing the 51sl core clock, are turned off. if an external crystal is used, the internal oscillator is turned off. memcsl, the external memory select signal, goes inactive unless it is configured as a general purpose i/o (i.e., unless bit 3 of configuration register 1 is a ``1''). ale and psenl are both forced low. ram contents are preserved. power down mode can only be exited via a reset. this reset may occur either from the rst pin, or an internally generated reset. see the 51sl hardware description (order no. y 272268) for a detailed de- scription of this reset. host interface the 51sl host interface is functionally compatible with the 8042 style upi interface. it consists of the pcdb0 7 data bus; the rdl, wrl, a0 and csl control signals; and the keyboard status register, input data register, and output data register. in ad- dition, a second address line, a1, has been added to decode a second set of registers for power manage- ment functions. these registers are identical to the keyboard registers. the host interface also includes a pcobf interrupt, gatea20, and host reset (rcl) outputs. two additional obf signals, auxobf1 and auxobf2 are available through firmware configura- tion of p34/t0 and p37/rdl respectively. 9
8xc51sl/low voltage 8xc51sl keyboard scan the interface to the keyboard scan logic includes 16 slew-rate-controlled, open drain scan out lines (kso0 15) and eight schmitt trigger sense lines (ksi0 7) with internal pullup resistors. ksi0 7 con- nect directly to port 0 of the 51sl cpu. the 16 scan out lines are controlled by the four low order bits of port 0. together kso0 15 and ksi0 7 form a key- board matrix. external keyboard and mouse interface industry standard pc-at compatible keyboards em- ploy a two wire, bidirectional ttl interface for data transmission. several sources also supply ps/2 mouse products that employ the same type of inter- face. to facilitate system expansion, the 51sl pro- vides four signal pins that may be used to implement this interface directly for an external keyboard and mouse. the 51sl has four high-drive, open-drain, bidirec- tional port pins that can be used for external serial interfaces, such as isa external keyboard and ps/2- type mouse interfaces. they are p30/sif00, p31/ sif01, p33/sif10, and p35/sif11. p33/sif10 is connected to the firmware configurable level/edge sensitive intl interrupt pin of the 51sl cpu. p30/ sif00 is connected to the edge sensitive sif0intl interrupt pin of the 51sl cpu. note that on the low voltage 8xc51sl these inputs are protected to 5.5v in order to provide compatibility with as many exter- nal keyboard and ps/2 mouse devices as possible. design considerations the low voltage characteristics of the low voltage 8xc51sl have indicated that additional care should be taken in selection of the crystal used in the oscil- lator circuit. in particular, series resistance of a crys- tal seems to have the largest effect on start-up time and steady state amplitude. consequently, the lower the series resistance the better, although medium to better quality crystals are generally more than ade- quate. 10
8xc51sl/low voltage 8xc51sl electrical specifications absolute maximum ratings * ambient temperature under bias b 40 cto a 85 c storage temperature b 65 cto a 150 c voltage on any pin to v ss b 0.5v to v cc a 0.5v power dissipation1.0w ** ** this value is based on the maximum allowable die tem- perature and the thermal resistance of the package. notice: this data sheet contains information on products in the sampling and initial production phases of development. it is valid for the devices indicated in the revision history. the specifications are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions 8xc51sl: t a (under bias) e 0 cto a 70 c, v cc ea 5v g 10%, v ss e 0v low voltage 8xc51sl: t a (under bias) e 0 cto a 70 c, v cc ea 3.3v g 0.3v, v ss e 0v 8xc51sl dc characteristics (over operating conditions) symbol parameter min max units test conditions v il input low voltage b 0.5 0.8 v (except xtal1, rst) v il1 input low voltage b 0.5 0.2 v cc b 0.1 (xtal1, rst) v ih input high voltage (except eal, 2.4 v cc a 0.5 v pcdb0 7, adb0 7, xtal1, rst, csl, rdl, wrl, loadren, a0, a1) v ih1 input high voltage (eal) v cc b 1.5 v cc a 0.5 v v ih2 input high voltage (pcdb0 7, 0.7 v cc v cc a 0.5 v adb00-7, xtal1, rst, csl, rdl, wrl, loadren, a0, a1) r p internal port resistors ksi0 7 5 20 k x v ol output low voltage b 0.5 0.4 v i ol e 16 ma bp pins (1) (except p27/led4) v ol1 output low voltage b 0.5 0.8 v i ol e 12 ma p27/led4, led0 3 v ol2 qb pins (2) , pcdb0 7, rcl, b 0.5 0.4 v i ol e 4ma adb0 7, gatea20, kso0 15, memcsl, ale, psenl, pcobf v oh output high voltage 2.4 v cc a 0.5 v i oh eb 60 m a qb pins, ale, psenl, pcobf v oh1 outut high voltage 4.0 v cc a 0.5 v i oh eb 2.0 ma memcsl, pcdb0 7, adb0 7 v oh2 output high voltage 4.0 v cc a 0.5 v i oh e 60 m a rcl, gatea20 11
8xc51sl/low voltage 8xc51sl 8xc51sl dc characteristics (over operating conditions) (continued) symbol parameter min max units test conditions i il logical 0 input current b 50 m av in e 0.4v qb (2) pins i li input leakage current g 10 m a0 k v in k v cc (bp and pure input pins except for ksi0 7, xtal1, and eal) i tl logical 1 to 0 transition b 1mav in e 2.0v current qb (2) pins i cc power supply current active mode at 16 mhz 38 ma idle mode at 16 mhz 15 ma power-down mode tbd m a low voltage 8xc51sl dc characteristics (over operating conditions) symbol parameter min max units test conditions v il input low voltage b 0.5 0.8 v (except xtal1, rst, ksi0 7) v il1 input low voltage b 0.5 0.2 v cc b 0.1 (xtal1, rst) v il2 input low voltage (ksi0 7) b 0.5 0.6 v ih input high voltage (except eal, 2.0 v cc a 0.5 v pcdb0 7, adb0 7, xtal1, rst) p30, p31, p33, p35) v ih1 input high voltage (eal) v cc b 1v cc a 0.5 v v ih2 input high voltage (pcdb0 7, 0.7 v cc v cc a 0.5 v adb0 7, xtal1, rst) v ih3 input high voltage 2.0 5.5 v (p30, p31, p33, p35) r p internal port resistors ksi0 7 5 20 k x v ol output low voltage b 0.5 0.4 v i ol e 16 ma bp pins (1) (except p27/led4) v ol1 output low voltage b 0.5 0.8 v i ol e 12 ma p27/led4, led0 3 v ol2 output low voltage b 0.5 0.4 v i ol e 4ma qb pins (2) , pcdb0 7, rcl, adb0 7, gatea20, kso0 15, memcsl, ale, psenl, pcobf v oh output high voltage v cc b 0.7 v cc a 0.5 v i oh eb 60 m a qb pins, ale, psenl, pcobf v oh1 output high voltage 2.4 v cc a 0.5 v i oh eb 2.0 ma memcsl, pcdb0 7, adb0 7 v oh2 output high voltage 2.4 v cc a 0.5 v i oh e 60 m a rcl, gatea20 i il logical 0 input current b 50 m av in e 0.4v qb (2) pins i li input leakage current g 10 m a0 k v in k v cc (bp and pure input pins except for ksi0 7, xtal1, and eal) 12
8xc51sl/low voltage 8xc51sl low voltage 8xc51sl dc characteristics (over operating conditions) symbol parameter min max units test conditions i tl logical 1 to 0 transition b 650 m av in e 1.5v current qb (2) pins i cc power supply current active mode at 16 mhz 25 ma idle mode at 16 mhz 10 ma power-down mode 175 m a notes: 1. bidirectional (bp) pins include p27/led4, p30/sif00, p31/sif01, p33/sif10, p36/sif11, memcsl, pcdb0 7, and adb0 7. 2. quasi-bidirectional (qb) pins include p20 6/a8 a14, p32/int0, p34/t0, p36/wrl, p37/rdl and p10 7/a0 7. 3. pure input pins include loadren, eal, a0, a1, csl, rdl, wrl, rst, ain0 3, and xtal1. ac characteristics explanation of the ac symbols each timing symbol has three or five characters. the first character is always ``t'' (for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. table 3 lists the characters and their mean- ings. example tavll e time for address valid to ale low. tllpl e time for ale low to psen low. table 3. ac symbol characters char. meaning a address c clock d input data h logic level high i instruction (program memory contents) l logic level low, or ale p psenl q output data r rdl signal t time v valid w wrl signal x no longer a valid logic level z float host-interface timing all outputs loaded with 50 pf symbol parameter min max units tar csl, a0/a1 setup to rd low 0 ns tra csl, a0/a1 hold after rdl high 0 ns tad csl, a0/a1 to data out delay 50 ns taw csl, a0/a1 setup to wrl low 0 ns twa csl, a0/a1 hold after wrl high 10 ns tdw data setup to wrl high 60 ns twd data hold after wrl high 5 ns tww minimum pulse width of wrl 50 ns trr rdl pulse width 50 ns trd rdl low to data out delay 50 ns tdf rdl high to data float delay 50 ns 13
8xc51sl/low voltage 8xc51sl external memory timing tclcl e 1 clock period, all outputs loaded with 50 pf symbol parameter min max units 1/tclcl oscillator frequency 2 16 mhz tlhll ale pulse width 2tclcl b 40 ns tavll address valid to ale low tclcl b 40 ns tllax address hold after ale low tclcl b 30 ns tlliv ale low to valid instruction in 4tclcl b 100 ns tllpl ale low to psenl low tclcl b 30 ns tplph psenl pulse width 3tclcl b 45 ns tpliv psenl low to valid instruction in 3tclcl b 105 ns tpxix input instruction hold after psenl high 0 ns tpxiz input instruction float after psenl high tclcl b 25 ns taviv address to valid instruction in 5tclcl b 105 ns tplaz psenl low to address float 10 ns trlrh p37/rdl pulse width 6tclcl b 50 ns twlwh p36/wrl pulse width 6tclcl b 50 ns trldv p37rdl low to valid data in 5tclcl b 100 ns trhdx data hold after p37/rdl 0 ns trhdz data float after p37/rdl 2tclcl b 50 ns tlldv ale low to valid data in 8tclcl b 100 ns tavdv address to valid data in 9tclcl b 100 ns tllwl ale low to p37/rdl or p36/wrl low 3tclcl b 25 3tclcl a 25 ns tavwl address valid to p36/wrl low 4tclcl b 50 ns tqvwx data valid before p36/wrl tclcl b 25 ns twhqx data hold after p36/wrl tclcl b 25 ns tqvwh data valid to p36/wrl high 7tclcl b 50 ns trlaz p37/rdl low to address float 0 ns twhlh p37/rdl or p36/wrl high to ale high tclcl b 25 tclcl a 25 ns 14
8xc51sl/low voltage 8xc51sl 272271 3 figure 3. host-interface read 272271 4 figure 4. host-interface write 272271 5 figure 5. external data memory read 15
8xc51sl/low voltage 8xc51sl 272271 6 figure 6. external data memory write 272271 7 figure 7. external program memory read 16
8xc51sl/low voltage 8xc51sl serial port timingeshift register mode test conditions: over operating conditions, load capacitance e 50 pf symbol parameter 16 mhz variable oscillator units oscillator min max min max txlxl serial port clock cycle time 750 12tclcl ns tqvxh output data setup to 492 10tclcl b 133 ns clock rising edge txhqx output data hold after 50 2tclcl b 117 ns clock rising edge txhdx input data hold after 0 0 ns clock rising edge txhdv clock rising edge to input data valid 492 10tclcl b 133 ns shift register mode timing waveforms 272271 8 external clock drive symbol parameter min max units 1/tclcl oscillator frequency 2.0 16 mhz tchcx high time 20 ns tclcx low time 20 ns tclch rise time 20 ns tchcl fall time 20 ns external clock drive waveform 272271 9 17
8xc51sl/low voltage 8xc51sl programming the otp the part must be running with a 4 mhz to 6 mhz oscillator. the address of a location to be pro- grammed is applied to address lines, while the code byte to be programmed in that location is applied to data lines. control and program signals must be held at the levels indicated in table 4. normally eal/v pp is held at a logic high until just before rcl/progl is to be pulsed. the eal/v pp is raised to v pp , rcl/progl is pulsed low and then eal/v pp is re- turned to v cc (also refer to timing diagrams). also, the loadren signal must be grounded when pro- gramming or verifying. note: exceeding the v pp maximum for any amount of time could damage the device permanently. the v pp source must be well regulated and free of glitches. definition of terms address lines: p10 p17, p20 p25, respective- ly for a0 a13. data lines: adb0 7. control signals: rst, gatea20, p26, p27, p32, p36, p37. program signals: rcl/progl, eal/v pp . programming algorithm refer to table 4 and figures 8 and 9 for address, data and control signals setup. to program the 87c51sl the following sequence must be exercised. 1. input the valid address on the address lines. 2. input the appropriate data byte on the data lines. 3. activate the correct combination of control sig- nals. 4. raise eal/v pp from v cc to 12.75v g 0.25v. 5. pulse rcl/progl 5 times. repeat 1 through 5 changing the address and data for the entire array or until the end of the object file is reached. table 4. otp programming modes mode rst gatea20 rcl/ eal/v pp p26 p27 p32 p36 p37 progl program code data h l ? 12.75v l h h h h verify code data h l h h l l l h h read signature byte h l h h l l l l l note that in the above table, to program code data on the low voltage 87c51sl v cc must be raised to 5v g 10%. in addition, all address lines, data lines, and control signals being driven to a ``high'' level must be raised to 5v g 10%. the rcl/progl sig- nal must pulse between 0v and 5v g 10%. to verify code data or read the signature bytes of the low voltage 87c51sl v cc must be set to 3.3v g 0.3v. in addition, all address lines and control sig- nals being driven to a ``high'' level must be raised to 3.3v g 0.3v. for the standard (5v version) of the 87c51sl v cc must always be at 5v g 10%, and all ``high'' volt- ages must meet the dc specs indicated in the dc characteristics section of this document. 18
8xc51sl/low voltage 8xc51sl 272271 10 * see table 4 for proper input on these pins. figure 8. programming/verifying the otp 272271 11 figure 9. programming signal's waveforms program verify program verify may be done after each byte that is programmed, or after a block of bytes that is pro- grammed. in either case a complete verify of the array will ensure that it has been programmed cor- rectly. reading the signature bytes the 8xc51sl and low voltage 8xc51sl each have three signature bytes in locations 30h, 31h, and 60h. to read these bytes, follow the procedure for eprom verify, but activate the control lines provid- ed in table 4 for read signature byte. location contents 87c51sl 83c51sl low voltage low voltage 87c51sl 83c51sl 30h 89h 89h 89h 89h 31h 58h 58h 58h 58h 60h bbh 3bh abh 2bh 19
8xc51sl/low voltage 8xc51sl otp programming and verification characteristics t a e 21 cto27 c; v cc e 5v g 10% for 87c51sl, 3.3v g 0.3v for low voltage 87c51sl (verification only). v cc for programming the low voltage 87c51sl must be 5.0v g 10%. v ss e 0v symbol parameter min max units v pp programming supply voltage 12.5 13.0 v i pp programming supply current 75 ma 1/tclcl oscillator frequency 4 6 mhz tavgl address setp to progl low 48tclcl tghax address hold after progl 48tclcl tdvgl data setup to progl low 48tclcl tghdx data hold after progl 48tclcl tehsh (enable) high to v pp 48tclcl tshgl v pp setup to progl low 10 m s tghsl v pp hold after progl 10 m s tglgh progl width 90 110 m s tavqv address to data valid 48tclcl telqv enable low to data valid 48tclcl tehqz data float after enable 0 48tclcl tghgl progl high to progl low 10 m s programming and verification waveforms 272271 12 20
8xc51sl/low voltage 8xc51sl a/d characteristics the 51sl includes a four-channel, 8-bit a/d con- verter. this a/d, with eight bits of accuracy, uses successive approximation with a switch capacitor comparator. it is designed to be used for sampling static analog signals (i.e., ideally suited for power management tasks such as battery voltage monitor- ing, etc.). the nominal conversion rate is 20 m sat 16 mhz. the analog high and low voltage refer- ences are connected to avref and avgnd, re- spectively. the four input channels, ain0 3 are connected from the package pins, unbuffered, to an analog multiplexer (on-chip). the absolute conver- sion accuracy is dependent upon the accuracy of avref. the specifications given assume adherence to the operating conditions section of this data sheet. testing is done at avref e 5.12v and v cc e 5.0v for the 8xc51sl, and at avref e 3.2v and v cc e 3.3v for the low voltage 8xc51sl. operating conditions v cc 8xc51sl 4.5v to 5.5v low voltage 8xc51sl 3.0v to 3.6v avref 8xc51sl 4.5v to 5.5v low voltage 8xc51sl 3.0v to 3.6v v ss , avss 0v ain0 3 avss to avref t a 0 cto a 70 c ambient f osc 2 mhz to 16 mhz a/d converter specifications (over operating conditions) parameter min typ max units resolution 255 256 levels 8 8 bits absolute error 0 g 1 lsb full scale error g 1 lsb zero offset error g 1 lsb non-linearity error 0 g 1 lsb differential non-linearity error 0 g 1 lsb channel to channel matching 0 g 1 lsb repeatability g 0.25 lsb temperature coefficients offset 0.003 lsb/ c full scale 0.003 lsb/ c differential non-linearity 0.003 lsb/ c off isolation b 60 db feedthrough b 60 db v cc power supply rejection b 60 db input resistance 750 1.2k x input capacitance 3 pf dc input leakage 0 3.0 m a 21
8xc51sl/low voltage 8xc51sl a/d glossary of terms absolute errore the maximum difference between corresponding actual and ideal code transitions. ab- solute error accounts for all deviations of an actual converter from an ideal converter. actual characteristice the characteristic of an ac- tual converter. the characteristic of a given convert- er may vary over temperature, supply voltage, and frequency conditions. an actual characteristic rarely has ideal first and last transition locations or ideal code widths. it may even vary over multiple conver- sions under the same conditions. break-before-makee the property of a multiplexer which guarantees that a previously selected channel will be deselected before a new channel is selected (e.g., the converter will not short inputs together). channel-to-channel matchinge the difference be- tween corresponding code transitions of actual char- acteristics taken from different channels under the same temperature, voltage and frequency condi- tions. characteristice a graph of input voltage versus the resultant output code for an a/d converter. it de- scribes the transfer function of the a/d converter. codee the digital value output by the converter. code centere the voltage corresponding to the midpoint between two adjacent code transitions. code transitione the point at which the converter changes from an output code of q, to a code of q a 1. the input voltage corresponding to a code tran- sition is defined to be that voltage which is equally likely to produce either of two adjacent codes. code widthe the voltage corresponding to the dif- ference between two adjacent code transitions. crosstalke see ``off-isolation''. dc input leakagee leakage current to ground from an analog input pin. differential non-linearitye the difference be- tween the ideal and actual code widths of the termi- nal based characteristic. feedthroughe attenuation of a voltage applied on the selected channel of the a/d converter after the sample window closes. full scale errore the difference between the ex- pected and actual input voltage corresponding to the full scale code transition. ideal characteristice a characteristic with its first code transition at v in e 0.5 lsb, its last code tran- sition at v in e (v ref b 1.5 lsb) and all code widths equal to one lsb. input resistancee the effective series resistance from the analog input pin to the sample capacitor. lsbeleast significant bite the voltage corre- sponding to the full scale voltage divided by 2 n , where n is the number of bits of resolution of the converter. for an 8-bit converter with a reference voltage of 5.12v, one lsb is 20 mv. note that this is different than digital lsbs since an uncertainty of two lsbs, when referring to an a/d converter, equals 40 mv. (this has been confused with an un- certainty of two digital bits, which would mean four counts, or 80 mv). monotonice the property of successive approxi- mation converters which guarantees that increasing input voltages produce adjacent codes of increasing value, and that decreasing input voltages produce adjacent codes of decreasing value. no missed codese for each and every output code, there exists a unique input voltage range which produces that code only. non-linearitye the maximum deviation of code transitions of the terminal based characteristic from the corresponding code transitions of the ideal char- acteristic. off-isolatione attenuation of a voltage applied on a deselected channel of the a/d converter. (also re- ferred to as crosstalk.) repeatabilitye the difference between corre- sponding code transitions from different actual char- acteristics taken from the same converter on the same channel at the same temperature, voltage and frequency conditions. resolutione the number of input voltage levels that the converter can unambiguously distinguish between. also defines the number of useful bits of information which the converter can return. sample delaye the delay from receiving the start conversion signal to when the sample window opens. sample delay uncertaintye the variation in the sample delay. sample timee the time that the sample window is open. sample time uncertaintye the variation in the sample time. 22
8xc51sl/low voltage 8xc51sl sample windowe begins when the sample capaci- tor is attached to a selected channel and ends when the sample capacitor is disconnected from the se- lected channel. successive approximatione an a/d conversion method which uses a binary search to arrive at the best digital representation of an analog input. temperature coefficientse change in the stated variable per degree centrigrade temperature change. temperature coefficients are added to the typical values of a specification to see the effect of temperature drift. terminal based characteristice an actual charac- teristic which has been rotated and translated to re- move zero offset and full scale error. v cc rejectione attenuation of noise on the v cc line to the a/d converter. zero offsete the difference between the expected and actual input voltage corresponding to the first code transition. data sheet revision summary the following differences exist between this data sheet (272271-002) and the previous version (272271-001). 1. data sheet status changed from ``product pre- view'' to ``advance information''. 2. title page item number three describing the glob- al interrupt enable change was removed. 3. title page item number two was corrected to read `` . . . was added in configuration register 1.'' 4. in the 8xc51sl dc characteristics section: the v oh test condition (i oh ) changed from b 0.8 ma to b 60 m a. the v oh1 test condition (i oh ) changed from b 4.0 ma to b 2.0 ma. v oh2 was added. the xtal1 and eal pins were added to the i li spec. the i tl spec changed from b 650 m ato b 1 ma. the i cc idle spec changed from 10 ma to 15 ma. the i cc power down spec changed from 100 m a to tbd. 5. in the low voltage 8xc51sl dc characteristics section: the v oh spec changed from 2.4v to v cc b 0.7 the v oh test condition (i oh ) changed from b 0.8 ma to b 60 m a. v oh2 was added. pins were clarified in the i li spec. the i tl test condition (v in ) was changed from tbd to 1.5v. the i cc power down spec changed from 100 m a to 175 m a. 6. the load capacitance for all timing tables was changed to 50 pf. 7. in the host interface timing section twd changed from 0 ns to 5 ns. 8. the external memory timing table changed as follows: spec. old new tlliv 4tclcl-50 4tclcl-100 tpliv 3tclcl-50 3tclcl-105 tpxiz tclcl-15 tclcl-25 taviv 5tclcl-50 5tclcl-105 trldv 5tclcl-50 5tclcl-100 tlldv 8tclcl-50 8tclcl-100 tavdv 9tclcl-50 9tclcl-100 tmvdv 9tclcl-50 removed tmviv 5tclcl-50 removed 9. in figures 5 and 7 the memcsl waveforms were removed. 10. clarification was added in the programming al- gorithm section. 11. in the a/d converter specifications section the minimum resolution was changed from 256 lev- els to 255 levels. 12. the data sheet revision summary was added. 23

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